Chip development involves passing through a multiplicity of production stages until a functional semiconductor chip is present. Development is a lengthy process that is always beset by errors, in particular as a result of the incorrect, unforeseeable interaction of the components and thus necessitates renewed development cycles.
In general, a first development step involves mapping the functions in subcircuits, and this may be followed by simulation by means of suitable software. Even at this stage development errors can be identified and eliminated. The structures proceeding from the subcircuits are subsequently refined further and further, so that, according to the present theoretical model, the hardware architecture is implemented in a layout design.
This generated layout design is compared with the applicable wiring and layout rules (DRC=Design Rule Control) with deviations from the rules being output as error data. These deviations may be brought about by exceptions in the layout configuration, so-called “dummy errors”, which are not implemented in the test algorithm, or by genuine errors. By virtue of these possibilities, the number of error messages is very high. For the further layout processing, however, it is essential to test all of the error data.
Proceeding from this first layout, a second layout design arises as a result of the elimination of the errors found or necessary alterations in the circuit arrangement, for example because predetermined parameters are not achieved. In those cases, such a redesign involves making only comparatively small changes at specific levels. The subsequent comparison of the second layout design, also referred to as redesign layout verification, is likewise effected according to the above-mentioned wiring and layout rules. In this comparison, too, all the “dummy errors” are once again concomitantly registered in the error data and subsequently have to be checked. Consequently, the outlay for the evaluation of the error data is very high even after a small layout change.
In practice, a plurality of redesigns are normally necessary in order to attain an error-free layout, which leads to an increase in costs, in particular due to redundant error checking steps.